New in 1.x (upcoming)

Already documented changes are available on the release branch at GitHub.

• VHDL common packages
• VHDL Simulation helpers
• New Entities
  • IP:ocram_sdp_wf
  • IP:ocram_tdp_wf
  • IP:cache_par2
  • IP:cache_cpu
  • IP:cache_mem
  • Simulation helper IP:ocram_tdp_sim
• Updated Entities
  • Interface of IP:cache_tagunit_par changed slightly.
  • New port “write-mask” in IP:ddr3_mem2mig_adapter_Series7.
  • New port “write-mask” in IP:ddr2_mem2mig_adapter_Spartan6.
  • Fixed IP:dstruct_deque
• New Testbenches
  • Testbench for IP:ocram_sdp_wf
  • Testbench for IP:ocram_tdp_wf
  • Testbench for IP:cache_par2
  • Testbench for IP:cache_cpu
  • Testbench for IP:cache_mem
• Updated Testbenches
  • Testbench for IP:ocram_sdp
  • Testbench for IP:ocram_esdp
  • Testbench for IP:ocram_tdp
  • Testbench for IP:sortnet_BitonicSort
  • Testbench for IP:sortnet_OddEvenSort
  • Testbench for IP:sortnet_OddEvenMergeSort
• New Constraints
• Updated Constraints
• Shipped Tool and Helper Scripts
• Python Infrastructure
  • Common changes
  • All Simulators
  • Aldec Active-HDL
  • GHDL
  • Mentor QuestaSim
  • Xilinx ISE Simulator
  • Xilinx Vivado Simulator
  • All Compilers
  • Altera Quartus Synthesis
  • Lattice Diamond (LSE)
  • Xilinx ISE (XST)
  • Xilinx ISE Core Generator
  • Xilinx Vivado Synthesis
• Continuous Integration
  • Implemented a simple Python infrastructe test on AppVeyor
• Documentation
  • Improved PDF rendering